Field of the Invention
The present invention relates to a semiconductor memory device, and more specifically to a matrix selection mechanism of a memory array.
Background Art
FIG. 4 is a circuit diagram illustrating a memory array of a related art EEPROM. One address is comprised of a memory word composed of a plurality of bits. A memory cell is comprised of a floating gate 401 for holding data and a control gate 402 for selecting a bit, and holds information of one bit therein. Since the reading of data from a memory normally starts from the MSB, i.e., the most significant bit side of data, MSB data is stored in a memory cell close to a word selector from the MSB side needed to be read earliest. The LSB of a data word, i.e., the least significant bit of data is stored in the farthest memory cell. In the process of manufacturing a memory array using an EEPROM, a checkerboard pattern in which data bits to be stored of memory cells adjacent to each other are brought into an inverted state, is required to be written in order to examine that data interference does not occur between adjacent memory cells.
As a method of writing a checkerboard pattern, there are a method of executing writing for each word, and a method of providing an even/odd-based selection function in each of row decoders of a memory array as proposed in a related art and writing bit-inverted data therein respectively.
[Patent Document 1]
Japanese Patent Publication No. Hei 4 (1992)-66080
[Patent Document 2]
Japanese Patent Application Laid-Open No. 2001-236795